1. Technical Field
The invention disclosed broadly relates to data processing techniques and more particularly relates to a method for controlling a distributed processing network and the processors and I/O units connected therewith.
2. Background Art
High speed general purpose data processing systems have been designed in the prior art to handle certain generic types of data processing problems. In particular, data processing systems designed to handle a variety of matrix manipulation problems, called array processors, have become exceedingly important in signal analysis where signals are characterized by means of digital filtering and fast Fourier transform analysis. A specific example of such a prior art system is shown in U.S. Pat. No. 4,041,461 by Gary L. Kratz, et al., assigned to the instant assignee, which discloses a signal analyzer system. In the prior art multiprocessing system represented by the Kratz, et al. patent, a control processor was required to continually issue specific command words to an arithmetic processor and a storage transfer controller and a typical problem solution would require that about 70 percent of the control processor's time be devoted to the preparation of commands dealing with arithmetic and memory to be carried out by the arithmetic processor or the storage transfer controller. In addition, when mutually dependent functions were to be performed by the arithmetic processor and the storage transfer controller, then the arithmetic processor had to indicate to the storage transfer controller when to unload the results of the arithmetic process, by communicating the completion status points between these dependent processors through the control processor itself. This resulted in impeding the total throughput of the system and rendering it difficult to expand to control additional dependent processors.
An improvement in distributed control for carrying out mutually dependent operations in a distributed processing system was accomplished by the U.S. Pat. No. 4,149,243 to Wallis, assigned to the instant assignee. Wallis described a distributed control architecture for a multiprocessor system which included the control processor operating on system programming instruments for executing system supervisory and task management functions. These functions were signaled over a control bus. Connected to the control bus is a first subunit processor and a second subunit processor, each for executing different types of data processing functions. A post and wait logic unit interconnected the first and second subunit processors to enable the direct signaling of the completion of mutually dependent operations. Thus, the control processor was free to initiate tasks to be performed by the first and second subunit processors and then the subunit processors would continue the execution of their respective operations, signaling post and wait control signals between each other as mutually dependent operations were completed.
A problem with the prior is that when there are three or more processors in a distributed processing network, the problem of distributing the overall complex function to be performed between the plurality of processors is time consuming, difficult to maintain, difficult to change. In order to program a distributed processing network, the programmer will assign component data processing tasks to each of the plurality of processors in the network. If the processing loads were to remain the same over time for each of the component data processors, then the programmer could expect that the overall complex function would be successfully executed in a reasonably efficient manner. However, because of changes over time and the data flowing through particular input/output units and because of the failure of particular data processing components in the network, the recovery of the system or the rebalancing of the load on the system requires the reassignment of some data processing tasks to other data processing components in the network. The problem with doing this is maintaining accountability of the new data processing element for the task it has just been assigned, of relating that physical data processing element to the task to be performed and identifying that data processor as the physical location for the performance of that task. Therefore it is very desirable to have the component data processing tasks which make up the overall complex data processing function to be performed, to be relocatable to diverse ones of the physical data processing elements in the network. This presents a tremendous problem for the programmer. In the prior art, virtually the only way to accommodate such a redistribution of tasks among the physical data processing units was to have a programmer manually reenter the control information, identifying the newly assigned data processing elements for the relocated tasks to be performed.